1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device such as a dual port memory comprising two types of memory arrays carrying out data transmission/reception between each other.
2. Description of the Background Art
In accordance with the multifunction and high performance of video equipments, high performance is also required by semiconductor memory devices for storing video signals as digital data, i.e. required by semiconductor memory devices for video such as video RAMs (Random Access Memory). A dual port memory is a semiconductor memory device that has the function to read and write in parallel and in series a plurality of data, employed as the semiconductor memory device for video.
FIG. 6 is a block diagram schematically showing the entire structure of a conventional dual port memory. The structure and operation of the conventional dual port memory will be explained hereinafter with reference to FIG. 6. In the following description, H level and L level correspond to power potential and ground potential, respectively.
Referring to FIG. 6, a conventional dual port memory 1 comprises a memory array 2 having a plurality of memory cells MC each formed of one MOS transistor TR and one capacitor C arranged in a matrix of rows and columns; a sense amplifier portion 3, a serial register 4, a serial bus line 5, a serial decoder 6, a counter 7, a serial data output terminal SDO, and a serial data input terminal SDI all provided for writing to and reading from memory array 2 a plurality of data in series; a row address buffer 11, a column address buffer 12, a row decoder 13, a column decoder 14, a data bus line 15, a parallel data output terminal PDO, and a parallel data input terminal PDI all provided for writing to and reading from memory array 2 a plurality of data in parallel.
Row address buffer 11 buffers address data AX0=AX7 of 8 bits, for example, forming an external row address signal AX to provide the same to row decoder 13. Similarly, column address buffer 12 buffers address data AY0-AY7 of 8 bits, for example, forming an external column address signal AY to provide the same to row decoder 14. Row decoder 3 is connected to all word lines WL included in memory array 2. Column decoder 14 is connected to all bit lines BL included in memory array 2 via data bus line 15. In memory array 2, the gates of respective transistors TR of the memory cells MC arranged along one row are connected to the same word line WL. The drains of respective transistors TR of the memory cells MC arranged along one column are connected to the same bit line BL.
Row decoder 13 applies a potential of H level only to the word line WL corresponding to the row specified by row address signals AX0-AX7 from row address buffer 11 (referred to as the selected word line hereinafter), out of all the word lines WL in memory array 2. This causes transistor TR in each memory cell MC arranged in the row selected by external row address signal AX to conduct, whereby capacitor C is electrically connected to bit line BL corresponding to the relative memory cell MC. Column decoder 14 electrically connects a plurality of bit lines BL corresponding to the column selected by column address signals AY0-AY7 from column address buffer 12 (referred to as the selected bit line hereinafter), out of the bit lines BL in memory array 2, to parallel data output terminal PDO and parallel data input terminal PDI via data bus line 15. Parallel data input terminal PDI is applied with parallel data of a predetermined bit length as the write data from an external source at the time of data writing. Parallel data output terminal PDO provides the output of data bus line 15 in parallel to an external source as the read out data at the time of data reading.
By the above described operations of row decoder 13 and column decoder 14, each capacitor C of memory cell MC connected to the selected word line WL and the selected bit line BL is charged or discharged according to the write data provided in parallel to parallel data input terminal PDI, at the time of data writing. As a result, the potential of the node of transistor TR and capacitor C in each memory cell MC connected to the selected word line WL and the selected bit line BL attains a potential of H level or L level according to the write data. That is to say, data is written simultaneously to all the memory cells MC of one row connected to the selected word like WL.
At the time of data reading, the potential of parallel data output terminal PDO is determined according to the potential of the node of transistor TR and capacitor C of each memory cell MC connected to the selected word line WL and selected bit line BL. That is to say, the stored data in the memory cells MC connected to the selected bit line BL and the selected word line WL appears at parallel data output terminal PDO via the corresponding bit line BL and data bus line 15. Thus, at the time of data reading, the stored data of the memory cells MC of one row connected to the selected word line WL are provided simultaneously from parallel data output terminal PDO.
The foregoing is the operation for writing and reading parallel data in the dual port memory. The operation of reading and writing serial data in a dual port memory will be explained hereinafter.
Row address buffer 11 and row decoder 13 operate in a manner similar to the case of parallel data writing and reading. Accordingly, the potential of only one word line WL selected from word lines WL in memory array 2 attains an H level. Column address buffer 12 responds to external column address signals AY0-AY7 for providing serial address signals SA0-SA7 of 8 bits, for example, for specifying each of the plurality of columns specified by column address signals AY0-AY7. Then, counter 7 responds to serial address signals SA0-SA7 for providing to serial decoder 6 serial column address signals SY0-SY7 of 8 bits, for example, for specifying sequentially one by one the columns of the address specified by external column address signal AY.
At the time of data reading, sense amplifier portion 3 amplifies the potential change generated at each bit line BL in memory array 2 and provides the same simultaneously to serial register 4. Serial register 4 temporarily stores the amplified output of sense amplifier portion 3 at the time of data reading. Serial decoder 6 controls electrical connection between serial bus line 5 and serial register 4 so that serial bus line 5 is provided with only the amplified output of the potential change generated at the bit lines BL corresponding to the columns selected by serial column address signals SY0-SY7 from counter 7, out of the temporarily stored amplified output in serial register 4. Serial column address signals SY0-SY7 provided from counter 7 specifies in time sequence the columns in memory array 2 one by one. This causes the amplified output of sense amplifier portion 3, temporarily stored in serial register 4, to be transferred one at a time to serial data output terminal SDO via serial bus line 5, at the time of data reading. At the time of data reading, a potential change corresponding to the potential of the node between transistor TR and capacitor C in each memory cell MC connected to the selected word line WL and the selected bit line BL is generated at the corresponding bit line BL. Accordingly, the stored data in memory cells MC along one row connected to the selected word line WL are provided one by one from serial data output terminal SDO sequentially to an external source.
At the time of data reading, a plurality of data to be written into all the memory cells MC connected to one word line WL in memory array 2 are applied serially from an external source as an H or L voltage signal to serial data input terminal SDI. These plurality of data are provided to serial bus line 5 one by one in time sequence. Serial decoder 6 controls the electrical connection between serial bus line 5 and respective bit lines BL in memory array 2, so that each data provided to serial bus line 5 is applied only to one bit line BL specified by serial column address signals SY0-SY7 from counter 7 via serial register 4 and sense amplifier portion 3, at the time of data writing. Serial column address signals SY0-SY7 provided from counter 7 specify the columns in memory array 2 one by one in time sequence. At the time of data writing, a plurality of data applied to serial data input terminal SDI from an external source are provided to bit line BL to which memory cells MC that will store the data are connected. As a result, external data are written into memory cells MC of one row connected to selected word line.
In addition to the above described functional components, the dual port memory comprises a clock generating circuit 16. Clock generating circuit 16 generates various clock signals controlling the operation timing of the above described components so that the above described circuit operations for reading and writing parallel data and serial data are implemented correctly, according to external control signals RAS, CAS, SC, DT. For example, the circuit operation for reading and writing serial data is controlled by an internal serial clock signal SC generated from clock generating circuit 16 in response to an external serial clock signal SC.
FIG. 7 indicates the circuit configuration of memory array 2, sense amplifier portion 3, serial register 4, and serial bus line 5.
Referring to FIG. 7, sense amplifier portion 3 comprises differential amplification type sense amplifiers 30. The number of sense amplifiers 30 is a half of the numbers of bit lines BL in memory array 2. Each sense amplifier 30 has two bit lines BL of memory array 2 connected. In memory array 2, the two bit lines BL connected to each sense amplifier 30 form one bit line pair attaining complementary potentials at the time of data reading and writing. The memory cells MC connected to one bit line BIT out of the two bit lines forming one bit line pair and the memory cells MC connected to the other bit line BIT are connected to different word lines WL. At the time of serial data reading, sense amplifier 30 amplifies the potential difference between one bit line BIT and the other bit line BIT.
FIG. 8 is a circuit showing a structure of sense amplifier 30. Referring to FIG. 8, sense amplifier 30 comprises a P channel MOS transistor 310 and an N channel MOS transistor 320 having the gates thereof connected to bit line BIT; and a P channel MOS transistor 330 and an N channel MOS transistor 340 having the gates thereof connected to bit line BIT. Transistor 310 and 320 are connected in series between signal lines 350 and 360. Similarly, transistors 330 and 340 are connected in series between signal lines 350 and 360. At the time of serial data reading and writing, power potential and ground potential are applied to signal lines 350 and 360, respectively. Therefore, at the time of serial data reading, if memory cell MC connected to the selected word line WL is connected to bit line BIT, and the potential of the node of transistor TR and capacitor C in this memory cell MC attains an H level, a slight charge is applied from capacitor C to bit line BIT, whereby the potential of bit line BIT rises according to this slight charge. In initiating data reading, bit line BIT and bit line BIT are equalized so that the potentials of bit line BIT and bit line BIT are identical. The potential rise in bit line BIT causes the generation of slight potential difference between bit line BIT and bit line BIT. Sense amplifier 30 operates to increase this potential difference between bit lines BIT and BIT.
More specifically, the potential rise of bit line BIT causes transistor 320 to become slightly conductive. As a result, there are potential drops in the gate node of transistors 330 and 340 and node d. In response to this potential drop, transistor 330 also becomes slightly conductive to generate potential rise in the gate node of transistors 310 and 320 and node c. Transistor 320 becomes heavily conductive by this potential rise to pull down the potentials of the gate node of transistors 330 and 340 and node d to the ground potential applied to signal line 360. Because transistor 330 also becomes heavily conductive in response, the potential of nodes c rises to the power potential applied to signal line 350. The potential of node d of transistors 310 and 320 and the potential of node c of transistors 330 and 340 are the output of sense amplifier 30. Thus, the potential of bit line BIT is pulled down to the power potential by sense amplifier 30 and applied to serial register 4. The potential of bit line BIT is pulled down to the ground potential by sense amplifier 30 and applied to serial register 4.
On the contrary, if memory cell MC connected to the selected word line WL is connected to bit line BIT, and the potential of the node of transistor TR and capacitor C of this memory cell MC attains an L level, slight charge is provided to this capacitor C from bit line BIT. Accordingly, the potential of bit line BIT drops according this slight charge. This causes transistor 310 to become slightly conductive in sense amplifier 30 to raise the potential of the gate node of transistors 330 and 340. In response, transistor 340 also becomes slightly conductive to drop the potential of the gate node of transistor 310 and 320. As a result, transistors 310 and 340 become heavily conductive, whereby the potential of node c is pulled down to the ground potential and the potential of node d is pulled up to the power potential.
Hence, the slight potential difference between bit lines BIT and BIT is amplified to the differential voltage between the power potential and the ground potential by sense amplifier 30. When memory cells MC connected to the selected word line WL are connected to bit lines BIT, the potential difference between bit lines BIT and BIT is amplified by either transistor 330 or 340 rendered conductive in each sense amplifier 30 since there is slight potential rise or drop in bit line BIT.
Referring to FIG. 7 again, serial register 4 comprises a plurality of flipflops 40 each provided corresponding to each sense amplifier 30. Flipflop 40 is connected to the corresponding sense amplifier 30 via two N channel MOS transistors 150 and 160. Flipflop 40 comprises two inverters 410 and 420 having each input and output terminal thereof connected to each other. As shown in FIG. 8, sense amplifier 30 comprises an output end (node c) of the bit line BIT side and an output end (node d) of the bit line BIT side. The output end of the bit line BIT side is connected to the input end of inverter 420 via transistor 150, and the output end of bit line BIT side is connected to the input end of inverter 410 via transistor 160. The gates of transistors 150 and 160 connected to all flipflops 40 in serial register 4 have the same activation signal applied. At the time of serial data reading and writing, this activation signal attains an H level to conduct transistors 150 and 160.
At the time of serial data reading, the outputs of the bit line BIT side and the bit line BIT side of sense amplifier 30 are latched at node a of the input end of inverter 420 and the output end of inverter 410, and node b of the input end of inverter 410 and the output end of inverter 420, respectively, in the corresponding latch circuit 40.
Serial bus line 5 comprises two data lines 100 and 110. Serial register 4 is connected to serial bus line 5 via separate N channel MOS transistors 120 and 130 for each flipflop 40. Data line 100 is connected to the input end of inverter 420 via transistor 120. Data line 110 is connected to the input end of inverter 410 via transistor 130. The gates of transistors 120 and 130 provided corresponding to each flipflop 40 are connected to serial decoder 6 via a common serial memory cell activation signal line 140. At the time of serial data reading and writing, serial decoder 6 provides a potential of the H level sequentially to each serial memory cell activation signal line 140. Therefore, at the time of serial data reading, the potential latched at node a and the potential latched at node b are transferred to data lines 100 and 110, respectively, for every flipflop 40 in serial register 4. The circuit operation of this transfer will be explained more specifically with reference to FIG. 9. FIG. 9 is a circuit diagram specifically showing the structure of flipflop 40.
Referring to FIG. 9, inverter 410 in flipflop 40 comprises a P channel MOS transistor 410a and an N channel MOS transistor 410b connected in series between power supply VC and ground GND. Similarly, inverter 420 comprises a P channel MOS transistor 420a and an N channel MOS transistor 420b connected in series between power supply VC and ground GND. At the time of serial data reading, transistors 120 and 130 are conductive when potential of an H level is applied to signal line 140. Data lines 100 and 110 are equalized to have identical potential to each other until a potential of the H level is applied to signal line 140. Data lines 100 and 110 are unequalized when potential of an H level is applied to signal line 140.
Therefore, if an H level potential and an L level potential are latched at nodes a and b, respectively, discharge is initiated from data line 110 towards ground GND via transistors 130 and 420b. This reduces the potential of data line 110 from the equalized potential (the H level). The potential of data line 110 is held at the potential (the H level) by potential of H level of node a. Thus, there is potential difference between data lines 100 and 110.
If an L level potential and an H level potential are latched at nodes a and b, respectively, discharge is initiated in data line 100 towards ground GND via transistors 120 and 410b. There is no discharge in data line 100. Therefore, the potential of data line 100 is held at the H level and the potential of data line 110 drops from the H level to generate potential difference between data lines 100 and 110.
Thus, at the time of serial data reading, there is potential difference between data lines 100 and 110 according to the latched data of flipflop 40. At the time of serial data reading, potential difference is sequentially generated between data lines 100 and 110 according to data temporarily stored in respective flipflops 40 in serial register 4. This potential difference is sensed and amplified by a sense amplifier not shown. The sensed and amplified signal of this sense amplifier is provided from serial data output terminal SDO in FIG. 6 as the readout data.
The description of operation of the circuit of FIG. 7 at the time of serial data reading is substantially included in the above description. Therefore, the operation of the circuit of FIG. 7 at the time of serial data writing will be explained hereinafter.
At the time of serial data writing, each data applied serially to serial data input terminal SDI in FIG. 6 as the write data is provided to data lines 100 and 110 as two potentials of complementary levels.
For example, when an H level potential is applied to data line 100 and an L level potential is applied to data line 110, the potentials of nodes a and b attain an H level and an L level by the potentials of data lines 100 and 110, respectively, in the flipflop 40 corresponding to the conductive ones of transistors 120, 130. In other words, one of the write data applied serially to serial data input terminal SDI is latched in one flipflop 40. The potentials latched in nodes a and b in this flipflop 40 are applied to sense amplifier 30 provided corresponding to this flipflop 40 via transistors 150 and 160, respectively. Because sense amplifier 30 operates as a latching circuit, the two potentials temporarily stored in the corresponding flipflop 40 are applied to bit lines BIT and BIT, respectively, without change in levels. As a result, the H level potential and L level potential latched in nodes a and b, respectively, in flipflop 40 corresponding to the conductive transistors 120 and 130 are provided to bit lines BIT and BIT connected to sense amplifier 30 provided corresponding to this flipflop 40. If memory cells MC connected to the selected word line WL are connected to bit lines BIT at this time, capacitor C of one of these memory cells MC is charged by potential of the H level provided to this bit line BIT. This causes an H level to be written to the node of transistor TR and capacitor C in this memory cell MC. Similarly, if memory cells MC connected to the selected word line WL are connected to bit lines BIT, capacitor C of one of these memory cells MC is discharged by potential of an L level provided to bit line BIT. This causes L level to be written into the node of transistor TR and capacitor C of this memory cell MC.
On the contrary, if an L level potential and an H level potential are provided to data lines 100 and 110, respectively, an L level potential and an H level potential are latched at nodes a and b, respectively, in flipflop 40 corresponding to the conductive ones of transistors 120, 130. In this case, if memory cells MC connected to the selected word line WL are connected to bit lines BIT, an L level is written into one of these memory cells MC. Similarly, if memory cells MC connected to the selected word line WL are connected to bit lines BIT, an H level is written into one of these memory cells MC.
At the time of serial data writing, an H level potential is applied to all the serial memory cell activation signal lines 140, as in the case of serial data reading. During the time period when the data to be written into memory cell MC connected to the selected word line WL and the arbitrary bit line BIT or BIT are applied to data lines 100 and 110, an H level potential is applied to serial memory cell activation signal line 140 connected to the gates of transistors 120 and 130 provided corresponding to sense amplifier 30 connected to the arbitrary bit line BIT or BIT. Therefore, at the time of serial data reading, each of the plurality of write data applied serially to serial data input terminal SDI is written into one of memory cells MC along one row connected to the selected word line WL. As a result, a plurality of write data are written into memory cells MC of one row connected to the selected word line WL.
Thus, at the time of serial data writing, the write data stored temporarily into each flipflop 40 in serial register 4 is transferred to memory array 2 via sense amplifiers 30. At the time of serial data reading, the readout data from memory cells MC of one row in memory array 2 are transferred to all the flipflops 40 in shift register 4. In other words, each flipflop 40 in serial register 4 functions as one memory cell storing the stored data of one memory cell MC in memory array 2. Therefore, serial register 4 functions as a memory array having a plurality of memory cells arranged in only the row direction. The number of memory cells is identical to the number of memory cells MC of one row in memory array 2. In the following description, serial register 4 and flipflop 40 are called a serial memory array and a serial memory cell, respectively.
The timing of the potential change in signal lines and nodes at the time of data transfer from memory array 2 to serial memory array 4 will be explained hereinafter with reference to FIG. 10. FIG. 10 is a timing chart for explaining the operation of the dual port memory for transferring data from memory array 2 to serial memory array 4.
Data reading from serial memory array 2 is carried out during the time period when external control signal RAS (FIG. 10(a)) is at an L level. To be more specific, a potential of H level is applied to the selected word line WL, as shown in FIG. 10(b), after the drop of external control signal RAS in memory array 2. Then, a power potential and a ground potential are applied to signal lines 350 and 360, as shown in FIGS. 10(c) and 10(d), respectively, in sense amplifier 30. This causes all sense amplifiers 30 in sense amplifier portion 3 to be activated.
Each potential of bit lines BIT (or BIT) connected to memory cells MC connected to the selected word line WL slightly rises or drops according to the stored data in the memory cell MC connected thereto, as shown in FIG. 10(e). This slight potential change is amplified by sense amplifier 30 being activated.
In other words, the potential of bit line BIT (or BIT) slightly rising in response to the rise of the potential of the selected word line WL rises to the power potential in response to the potential rise of signal line 350, as shown in curve 1 of FIG. 10(e). Conversely, the potential of bit line BIT (or BIT) dropping in response to the rise of the potential of the selected word line WL drops to the ground potential in response to the drop of the potential of signal line 360, as shown in curve 2 of FIG. 10(e).
The potential of bit line BIT (or BIT) which is the pair of the above-mentioned bit line BIT (or BIT) having a slight rise in potential is brought to the ground potential in response to the activation of sense amplifier 30. The potential of bit line BIT (or BIT) that is the pair of the bit line BIT (or BIT) where potential slightly drops is brought to the power potential in response to the activation of sense amplifier.
The activation signal applied to the gates of transistors 150 and 160 (referred to as the data transfer signal hereinafter) is at an H level for a constant short time period, as shown in FIG. 10(f). That is to say, transistors 150 and 160 conduct only during this time period, whereby each output of all the sense amplifiers 30 in sense amplifier portion 3 is transmitted to the corresponding serial memory cell 40. Therefore, stored data of each serial memory cell 40 in serial memory array 4 is switched to a new data applied from sense amplifier 30 during the time period when the data transfer signal is at an H level, as shown in FIG. 10(g). When writing the output of sense amplifier 30 into the corresponding serial memory cell 40 is completed, the potential of the selected word line WL attains an L level. In response, the two bit lines BIT and BIT forming a bit line pair are equalized, whereby the potentials of all bit lines BIT, BIT return to an intermediate potential between the power potential and the ground potential. At the same time, the potentials of signal lines 350 and 360 of FIG. 8 attain the ground potential and the power potential, respectively, to deactivate sense amplifier 30.
The timing of the potential change in signal lines and nodes at the time of transferring data from serial memory array 4 to memory array 2 will be explained hereinafter with reference to FIG. 11. FIG. 11 is a timing chart for explaining the operation of the dual port memory for transferring data from serial memory array 4 to memory array 2.
The data transfer from serial memory array 4 to memory array 2 is also carried out during the time period when external control signal RAS (FIG. 11(a)) is at an L level. The data transfer signal is at an H level for a constant short time period after external control signal RAS drops, as shown in FIG. 11(f). The write data stored in each serial memory cell 40 is applied to the corresponding sense amplifier 30 during this time period.
Sense amplifier 30 is activated after the rise of the data transfer signal. More specifically, signal lines 350 and 360 of FIG. 8 are supplied with the power potential and the ground potential, as shown in FIG. 11(c) and 11(d), respectively. The write data applied to sense amplifier 30 from serial memory cell 40 is latched in sense amplifier 30. The potentials of the two bit lines BIT and BIT forming each bit line pair change complementarily according to the data latched at the connected sense amplifier 30, as shown in FIG. 11(e). That is to say, one potential out of the two bit lines BIT and BIT forming a bit line pair (curve 1 of FIG. 11(e)) attains the power potential in response to the rise of the potential of signal 350, and the other potential (curve 2 of FIG. 11(e)) attains the ground potential in response to the drop of the potential of signal line 360.
An H level potential is provided to the selected word line WL, as shown in FIG. 11(b). As a result, each of memory cells MC of one row connected to selected word line WL has a data written according to the potential of the corresponding bit line BIT or BIT. When writing data to memory array 2 is completed, the potential of the selected word line WL returns to the L level. In response, the two bit lines BIT and BIT forming a bit line pair are equalized, so that the potentials of all bit lines BIT and BIT return to the aforementioned intermediate potential. At the same time, the potentials of signal lines 350 and 360 of FIG. 8 return to the ground potential and the power potential, respectively, to deactivate sense amplifier 30.
The timing of the potential change in signal lines and nodes at the time of transferring data from data bus line 5 to serial memory array 4 will be explained hereinafter with reference to FIG. 12. FIG. 12 is a timing chart for explaining the operation of the dual port memory for transferring data from data bus line 5 to serial memory array 4.
At the time of transferring data from data bus line 5 to serial memory array 4, a potential of H level is applied from serial decoder 6 to one of serial memory cell activation signal lines 140 for a constant short time period, as shown in FIG. 12(b). During this short time period, data lines 100 and 110 are electrically connected to nodes a and b in serial memory cell 40 provided corresponding to transistors 120 and 130 having the gates thereof connected to the above mentioned one signal line 140. As a result, the potentials of nodes a and b attain potentials corresponding to the data applied to data lines 100 and 110 (FIG. 12(a)). In other words, the stored data in serial memory cell 40 is switched to a new data from data bus line 5 during the above-mentioned short time period, as shown in FIG. 12(c).
The timing of the potential change in signal lines and nodes at the time of transferring data from serial memory array 4 to serial bus line 5 will be explained hereinafter with reference to FIG. 13. FIG. 13 is a timing chart for explaining the operation of the dual port memory for transferring data from serial memory array 4 to data bus line 5.
A potential of H level is applied to one of serial memory cell activation signal lines 140 for a constant short time period, also at the time of data transfer from serial memory array 4 to serial bus line 5, as shown in FIG. 13(b). Data lines 100 and 110 are equalized until a potential of H level is supplied to any one signal line 140. Therefore, the potentials of data lines 100 and 110 both are at an H level, till the potential of the one signal line 140 rises, as shown in FIG. 13(a). When the potential of signal line 140 rises, data lines 100 and 110 are unequalized. Therefore, in response to the stored data of serial memory cell 40 provided corresponding to transistors 120 and 130 having the gates connected to signal line 140 (FIG. 13(c)), one potential (curve 2) of either of data lines 100 and 110 drops from the H level, and the other potential (curve 1) is held at the H level.
The potential change of data lines 100 and 110 and nodes a and b in serial memory cell 40 generated when data is transferred between data lines 100 and 110 and serial memory cell 40, and the potential change of nodes a and b in serial memory cell 40 generated when data is transferred between serial memory cell 40 and sense amplifier 30 will be explained in more detail with reference to FIG. 14.
FIG. 14 is a circuit diagram showing the structure of the circuit portions provided corresponding to an arbitrary bit line pair for serial data reading and writing. Sense amplifier 30 and serial memory cell 40 in FIG. 14 are represented by the circuit diagrams of FIGS. 8 and 9, respectively.
It is assumed that an H level potential and an L level potential are latched at nodes a and b, respectively, in serial memory cell 40 of FIG. 14, just before data is transferred from data lines 100 and 110 to serial memory cell 40. In this case, the following phenomenon is generated in case transistors 120 and 130 become conductive when an L level potential and an H level potential are applied to data lines 100 and 110, respectively, as write data.
Since transistors 410a and 410b are conductive just before transistors 120 and 130 conduct, current flowing from data line 110 to ground GND via transistor 420b and current flowing from power supply VC to data line 100 via transistor 410a are initiated right after transistors 120 and 130 conduct. This causes the potential of data line 110 to drop from the H level, and the potential of data line 100 to rise from the L level. It should be noted that the current capacity of data line 110 and the sizes of transistors 420a and 420b are set in advance, so that the magnitude of current applied from data line 110 of H level to node b of L level is sufficiently greater than the current flowing from node b to ground GND via the conductive transistor 420a, and that the magnitude of current applied from node b of H level to data line 110 of L level is sufficiently greater than the current flowing from power supply VC to node b via the conductive transistor 420a. Also, the current capacity of data line 100 and the sizes of transistors 410a and 410b are set in advance, so that the magnitude of the current applied from data line 100 of H level to node a of L level is sufficiently larger than the current flowing from node a to ground GND via the conductive transistor 410b, and the magnitude of the current provided from node a of the H level to data line 100 of the L level is sufficiently larger than the current flowing from power supply VC to node a via the conductive transistor 410a.
Therefore, although the potential of data line 110 slightly drops from the H level right after transistors 120 and 130 become conductive, the potential of data line 110 returns to the H level since the potential of node b immediately attains an H level by the current provided from data line 100. Similarly, the potential of data line 100 slightly rises from the L level right after transistors 120 and 130 become conductive, and then returns to L level since the potential of node a immediately attains an L level by the current drawn from node a to data line 110.
A similar phenomenon occurs when an L level potential and an H level potential are latched at nodes a and b, respectively, right before transistors 120 and 130 conduct, and when the potentials of data lines 100 and 110 attain the H and L levels, respectively.
More specifically, right after the conduction of transistors 120 and 130, the potential of data line 100 drops slightly due to the current flowing from data line 100 to ground GND via transistors 120 and 410b, and the potential of data line 110 rises slightly due to the current flowing from power supply VC to data line 110 via transistors 420a and 130. Then, the potential of data line 100 returns to the H level, due to the potential of node a attaining the H level by the current applied from data line 100 to node a. Simultaneously, the potential of data line 110 returns to the L level, due to the potential of node b attaining the L level by the current drawn from node b to data line 110.
At the time of serial data writing, if the potential levels of data lines 100 and 110 differ from those latched already in nodes a and b (that is to say, the write data externally applied to data lines 100 and 110 differ from the data already stored in serial memory cells 40), the potential (curve 1) of the data line 100 or 110 which is at the H level slightly drops in response to the rise of the potential of signal line 140, and the potential (curve 2) of the data line of the L level slightly rises in response to the rise of the potential of signal line 140.
The transfer of data from serial memory cell 40 to data lines 100 and 110 will be explained.
If H level and L level potentials are latched in advance in nodes a and b in FIG. 14, for example, current flows from data line 110 to node b via transistor 130 during the time period transistors 120 and 130 are conductive. Therefore, the potential of node b is held at a level slightly higher than an L level during this time period. This current causes the potential of data line 110 to drop to result in potential difference between data lines 100 and 110. When transistors 120 and 130 return to the non-conductive state, the current path is cut off, whereby the potential difference between data lines 100 and 110 are maintained. The potential of node b returns to the L level due to the current flowing from node b to ground GND via transistor 420b.
Conversely, if an L level potential is latched in node a, the potential of node a is held at a level slightly higher than the L level, due to the current flowing from data line 100 to node a via transistor 120 during the conductive time period of transistors 120 and 130. The potential of data line 110 gradually drops. Therefore, when transistors 120 and 130 return to the non-conductive state, the potential of node a returns to the L level due to the current flowing to transistor 410b, and the potential of data line 100 is held at the dropped potential.
Hence, at the time of data transfer from serial memory cell 40 to data lines 100 and 110, the potential of the node a or b having an L level potential latched temporarily rises during the time period when signal line 140 is at an H level potential, as shown in curve 1 of FIG. 13(c).
The transfer of data from serial memory cell 40 to the corresponding sense amplifier 30 will be explained hereinafter.
In FIG. 14, the following phenomenon will occur right after the conduction of transistors 150 and 160, when an H level potential and an L level potential are latched at nodes a and b, respectively, for example, just before the transfer of data from serial memory cell 40 to sense amplifier 30.
Sense amplifier 30 is activated after the rise of the data transfer signal, as shown in FIG. 11. This means that signal lines 350 and 360 attain the ground potential and the power potential right after transistors 150 and 160 conduct. Therefore, right after the conduction of transistors 150 and 160, transistors 330 and 320 temporarily conduct in sense amplifiers 30. As a result, current flows from node a to signal line 350 via transistors 150 and 330, and current flows from signal line 360 to node b via transistors 320 and 160. This causes the potential of node a to slightly drop and the potential of node b to slightly rise. It should be noted that sense amplifier 30 is activated during the time period when the data transfer signal attains an H level. Therefore, the current flowing from node a to the lower potential side and the current flowing from the higher potential side to node b are cut off right after the potentials of nodes a and b begin to drop or rise, respectively. As a result, the potentials of nodes a and b return to the H and L levels, respectively.
Conversely, if an L level potential and an H level potential are latched at nodes a and b, respectively, just before data is transferred from serial memory cell 40 to sense amplifier 30, a phenomenon opposite to the above described phenomenon occurs.
More specifically, right after transistors 150 and 160 conduct, the potential of node a slightly rises temporarily by the current flowing from signal line 360 to node a via transistors 340 and 150, and the potential of node b slightly drops temporarily by the current flowing from node b to signal lines 350 via transistors 160 and 310.
Thus, at the time of data transfer from serial memory cell 40 to the corresponding sense amplifier 30, the potential (curve 2) of node a or b having an H level latched drops temporarily right after the rise of the data transfer signal, and the potential (curve 1) of the other node slightly rises temporarily right after the rise of the data transfer signal, as shown in FIG. 11(g).
The value in the parenthesis of FIG. 14 is the ratio of each channel width W of the transistors forming serial memory cell 40 and the transistors forming sense amplifier 30 to the channel width of other transistors. The ratio of the channel width W set in FIG. 14 is only an example of the channel width setting of the transistors forming sense amplifier 30 and serial memory cell 40 in a conventional dual port memory.
As described in the foregoing, in a conventional semiconductor memory device having serial data writing/reading function, data is transferred between two types of memory arrays and between one of these two memory arrays and a bus line of data input/output.
The following problems are encountered in such a conventional semiconductor memory device.
To improve the readout speed of serial data in the dual port memory of FIG. 6, the data transfer speed from sense amplifier 30 to the corresponding serial memory cell 40 and the data transfer speed from serial memory cell 40 to data lines 100 and 110 in FIG. 7 should be improved.
In the case of transferring data from sense amplifier 30 to serial memory cell 40, the potentials of nodes c and d attain complementary logic levels corresponding to data readout from memory cell MC in memory array 2 to bit line BIT or BIT. The potentials of nodes a and b are held at the potentials applied from data lines 100 and 110 or from sense amplifier 30. Therefore, the potentials of nodes a and b may differ from those of nodes c and d, respectively. The case will be considered hereinafter where transistors 150 and 160 conduct when an H level potential and an L level potential are latched at nodes a and b, respectively, and when the potentials of nodes c and d are at L and H levels, respectively.
When transistors 150 and 160 conduct, node a has current drawn by transistors 340 to signal line 360 which is at the power potential, and current applied from power supply VC by transistor 410a. Simultaneously, node b has current provided from signal line 350 which is at the power potential by transistor 310, and current drawn by transistor 420b to ground GND. Therefore, the potentials of nodes a and b will immediately drop and rise, respectively, but will not be equal to the potential level of nodes c and d. The potentials of nodes a and b are applied to the gate node of transistors 420a and 420b, and to the gate node of transistors 410a and 410b, whereby transistors 410a and 410b will become non-conductive and conductive afterwards, respectively, in response to the rise in potential of node b. Transistors 420a and 420b will become conductive and non-conductive, respectively, afterwards, in response to the drop in potential of node a. Therefore, the potentials of nodes a and b eventually stabilize at the H level and the L level, respectively.
Therefore, in order to speed data transfer from sense amplifier 30 to serial memory cell 40, the current flowing to node a from power supply VC via transistor 410a and the current flowing from node b to ground GND via transistor 420b should be reduced to obtain a faster potential drop in node a and a faster potential rise in node b.
The case will be considered where transistors 150 and 160 conduct when an L level potential and an H level potential are latched at nodes a and b, and when nodes c and d are at the H level and the L level, respectively.
When transistors 150 and 160 conduct, the current flowing to ground GND from node a via transistor 410b prevents the potential of node a from being immediately brought to an H level, and the current flowing to node b from power supply VC via transistor 420a prevents the potential of node b from being immediately brought to the L level. To transfer data from sense amplifier 30 to serial memory cell 40 at a high rate, therefore, the current flowing from node a to ground GND via transistor 410a and the current flowing from power supply VC to node b via transistor 420a should be reduced to improve the potential rise speed of node a by the current provided to node a from signal line 350 and to improve the potential drop speed of node b by the current flowing from node b to signal line 360.
It can be understood from the foregoing that the current flowing between the source and drain of each of transistors 410a, 410b, 420a and 420b at the time of conduction should be reduced to improve the data transfer speed from sense amplifier 30 to serial memory cell 40. For this purpose, the size, for example the channel width W of each of transistors 410a, 410b, 420a, and 420b, should be reduced. The magnitude of current flowing between the source and drain of a MOS transistor turned on increases according to channel width W of the MOS transistor. The drive capability of a MOS transistor is the amount of current that can flow across the source and drain thereof.
FIG. 15 is a sectional view and a plan view of an MOS transistor. FIGS. 15(a) and (b) show relative MOS transistors having a short channel length and a long channel length, respectively.
Referring to FIG. 15, the MOS transistor comprises a conductor layer (shaded in the drawing) as a gate G formed with a constant width of L on a semiconductor substrate 500, and two impurity diffusion layers (dotted in the drawing) at semiconductor substrate 500 at right angles with the conductor layer, as the source S and drain D. The channel of the MOS transistor is formed in the conductive layer sandwiched by the two impurity diffusion layers. Channel current flows through this portion. The channel length of the MOS transistor corresponds to the width of the conductor layer, i.e. the gate width L. The channel width of the MOS transistor corresponds to the width of the impurity diffusion layer, i.e. the width W of the source/drain.
The cross sectional area in the direction (shown by a chain dotted line B in the figure) at right angles with the channel current flow of the channel region (enclosed in bold line in the figure) becomes greater according to the increase of channel width W. Therefore, if the voltage between the source and drain is constant, the magnitude of current flowing across the source and drain is proportional to the channel width W.
It can be appreciated by comparing FIGS. 15(a) and (b) that the resistance in the direction parallel to the channel current flow in the channel region increases according to the channel length L. Therefore, if the voltage across the gate and source is constant, the magnitude of current flowing across the source and drain is inversely proportional to channel length L.
FIG. 16 is a graph showing the relation between a current I.sub.DS across the source and gate and a voltage V.sub.GS across the gate and source of two MOS transistors having different channel lengths (i.e. gate width) L. Curves 1 and 2 show an N channel MOS transistor having a small gate width L, and an N channel MOS transistor having a great gate length L, respectively.
It can be appreciated from FIG. 16 that a transistor of a smaller gate width L has a greater change in current I.sub.DS flowing across the source and drain when the gate potential is raised while the source is grounded in an N channel MOS transistor. On comparing two arbitrary MOS transistors having the same voltage between source and gate, the current across the source and drain of a MOS transistor of a small gate width L is greater than that of a MOS transistor having a large gate width L. This means that the drive capability of a MOS transistor is adjustable by changing the gate width L.
In the case of comparing two MOS transistors having different thicknesses T of gate G, the electric field generated at the channel region of the transistor with a thin gate G thickness T is greater than that of the transistor with a thick gate G thickness T, if the voltage V.sub.GS applied across the gate and source is identical. This means that the current across the source and the drain increases as the thickness T of gate G is thinner. The drive capability of a MOS transistor can also be adjusted by changing the thickness T of gate G.
If the transistor operation speed of data from sense amplifier 30 to serial memory cell 40 is improved according to the decrease of the drive capability of transistors 410a, 410b, 420a and 420b, data transfer from serial memory array 40 to serial bus line 5 can not be carried out appropriately.
The case is considered where transistors 120 and 130 conduct when an H level potential and an L level potential are latched at nodes a and b, respectively. When transistors 120 and 130 conduct, the potential of data line 110 begins to drop by the current flowing from data line 110 to ground GND via transistors 130 and 420b. As a result, the potential difference generated between data lines 100 and 110 is amplified by a sense amplifier as the readout data. To readout data stored temporarily in serial memory cell 40 to data lines 100 and 110 at a high speed, the current flowing from data line 110 to ground GND via transistors 130 and 420b should be increased to increase the rate of drop of potential of data line 100. In other words, current flowing across transistor 420b should be increased.
In the case transistors 120 and 130 conduct when an L level potential and an H level potential are latched at nodes a and b, respectively, the potential of data line 100 begins to drop by the current flowing from data line 110 to ground GND via transistors 120 and 410b, opposite to the above-described case. Therefore, the potential drop speed of data line 110 should be improved by increasing the current flowing to ground GND via transistor 410b, in order to transfer data at a high rate from serial memory cell 40 to data lines 100 and 110.
It can be understood from the foregoing that the size, for example the channel width W of N channel transistors 410b and 420b in serial memory cell 40 should be increased to improve the transfer rate of data from serial memory cell 40 to serial bus line 5.
However, if transistors 410b and 420b are designed in small sizes in order to speed data transfer from sense amplifier 30 to serial memory cell 40, the potential drop speed of data line 100 or 110 becomes slower since the current flowing across transistors 410b and 420b is small at the time of data transfer from serial memory cell 40 to data lines 100 and 110. As a result, the transfer rate of data from serial memory cell 40 to data lines 100 and 110 is decreased, and data may not be readout properly due to potential difference between data lines 100 and 110 being reduced.
If the size of transistors 410b and 420b are increased to facilitate data transfer from serial memory cell 40 to serial bus line 5, the transfer rate of sense amplifier 30 to serial memory cell 40 is decreased, and transfer of data from data lines 100 and 110 to serial memory cell 40 may not be carried out appropriately.
In FIG. 14, if transistors 120 and 130 conduct when the potentials of data lines 100 and 110 are at an L level and an H level, respectively, by the write data, and potentials of nodes a and b are at an H level and an L level by the data previously latched at serial memory cell 40, current flows from data line 110 to ground GND via transistors 130 and 420b and current flows from power supply VC to data line 100 via transistors 410a and 120. Accordingly, the current flowing from power supply VC to node a via transistor 410a prevents the potential of node a from dropping to the L level. Similarly, the current flowing from node b to ground GND via transistor 420b prevents the potential of node b from rising to the H level. Therefore, in order to facilitate data transfer from data lines 100 and 110 to serial memory cell 40, the current flowing from power supply VC to node a via transistor 410a and the current flowing from node b to ground GND via transistor 420b should be minimized. In other words, the size, channel width W for example, of transistors 410a and 420b should be as small as possible.
In the case transistors 120 and 130 conduct when the potentials of data lines 100 and 110 are at the H and L level, respectively, and the potential of nodes a and b are at the L and H level, respectively, the current flowing from node a to ground GND via transistor 410b prevents the potential of node a from rising to the H level by the potential of data line 100, and the current flowing from power supply VC to node b via transistor 420a prevents the potential of node b from dropping to the L level by the potential of data line 110. In order to facilitate data transfer from data lines 100 and 110 to serial memory cell 40, therefore, the current flowing from node a to ground GND via transistor 410b and the current flowing from power supply VC to node via transistor 420a should be as small as possible. In other words, the size, the channel width W for example of transistors 410a and 420b should be as small as possible.
It can be understood from the foregoing that the size, the channel width W, for example, of transistors 410a, 410b, 420a and 420b forming serial memory cell 40 should be reduced in order to facilitate data transfer from data lines 100 and 110 to serial memory cell 40. Such a size setting is opposite to that of facilitating data transfer from serial memory cell 40 to data lines 100 and 110. If the size of the transistors in serial memory cell 40 are defined to facilitate data transfer from serial memory cell 40 to serial bus line 5, data transfer from serial bus line 5 to serial memory cell 40 may not be carried out appropriately. This generates the problem that the data transfer rate from serial bus line 5 to serial memory cell 40 is decreased, and that the potentials of nodes a and b will not reach the potential levels of data lines 100 and 110, respectively, whereby data will not be transferred from serial bus line 5 to serial memory cell 40.
Thus, data transfer from sense amplifier 30 to the corresponding serial memory cell 40, and data transfer from serial memory cell 40 to serial bus line 5 cannot be implemented with ease for serial data reading. Also, data transfer from serial bus line 5 to serial memory cell 40 for serial data writing and data transfer from serial memory cell 40 to serial bus line 5 for serial data reading cannot be implemented together with ease. In a conventional semiconductor memory device comprising serial data reading/writing function, therefore, it was difficult to improve the serial data reading rate and both the serial data reading/writing rate.
In a conventional semiconductor memory device, two data lines (data lines 100 and 110 in FIG. 14) are used for data input from an external source and data output to an external source. This will increase the occupying area of serial bus line 5 on dual port memory chip 1 of FIG. 6, for example, to reduce the area allocated for other functional components in chip 1. Accordingly, increase in memory capacity of semiconductor memory devices is hindered.